![]() A common mistake in probing is referencing to the wrong ground point (black dots). In figure 10a, Red stars indicate recommended probe locations for VGS and VDS measurements. Low inductance probing technique is required for assessing over voltage risk. Minimize controller signal and power loop overlapįigure 8: Recommended PowerPhase Layout Figure 9: Separating high power loop (red) and signal loop (grey) – See more at:.Thermal vias are most effective in reduce junction temperature when placed underneath the package. If possible, place driver IC close to G2 pin for minimal low side gate bounce. By placing input decoupling capacitance and gate signals on opposite sides, their interferences can be minimized. In Figure 9, red shaded high current path creates induced noise voltage from parasitic inductances. The recommended layout show in figure 8’s goal is to separate high current path from the signal path. Figure 7: Different input decoupling capacitor placements and power loop Placement PL2 and P元 is approximated to be 1.4nH. On a typical 4-layer 40 mil board thickness with 2nd Fig7layer as ground plane, power loop inductance for placement PL1 is approximated to be 1.3nH including package contribution. Both placements utilized inner PCB layers for magnetic field cancellation. The next best placements will be either placing directly below (P元 in Figure 7) or in line with the PowerPhase (PL2 in Figure 7). Figure 5: High di/dt power loop Figure 6: High and low side switching and phase node voltageĭue to the close proximity of input voltage pin and ground pin on the PowerPhase footprint, minimal power loop inductance (PL1 in Figure 7) can be achieved by placing decoupling capacitor next to pin 4. One way to reduce ringing energy, power loop inductance needs to be minimized. Total power loop inductance is formed Fig5by the package and the layout inductance between the input decoupling capacitor. The power loop is the high current di/dt path (Figure 6). Parasitic power loop inductance and low side output capacitance (Figure 5) forms a resonant circuit causing phase node ringings and power losses. During the high side switching transitions, the current is provided by the decoupling capacitor. Phase node voltage overshoot can be very severe. Figure 3: SO-8FL parasitic inductance Figure 4: PowerPhase parasitic inductanceĭue to the kelvin connection, drain current transition speed di/dt has increased. PowerPhase also reduced switching time by utilizing high side kelvin connection which bypassed clip inductance in driver loop. PowerPhase solution’s inductance is reduced by half (Figure 4). SO-8FL solution (Figure 3) has a minimal of 1nH total package inductance from two interconnect clip parasitic Fig3inductances. In synchronous buck converter, two MOSFET devices form a half-bridge configuration. Figure 2: PowerPhase package layer-by-layer Low side die is flipped with source attached to the lead frame and high side die has a kelvin source connection (Figure 2). PowerPhase is dual dies device in a half-bridge configuration. Traditional SO8-FL package has MOSFET’s drain connection attached to the lead Fig1frame and source clip bonded (Figure 1). SO8-FL and PowerPhase packages are 5 x 6 mm2. Structural Differences in SO8-FL and PowerPhase packages Package Figure 1: SO-8FL package layer-by-layer This application note points out some of the power MOSFET application concerns in modern high power density voltage regulator. While the old solutions of using SO8-FL are less efficiency new integrated packages, layout requirements were less critical and switching frequency limited by the package parasitic inductance. With advancement of Si technology and packaging, MOSFET can achieve a switching transition of less than 10nS, which is equivalent to di/dt of more than 1A/nS New PowerPhase packages enable faster switching by minimizing package parasitic inductances. Most of voltage regulators are still using discrete solutions like SO8-FL 5 x 6 mm2 package.
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